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Ιδρυματικό Αποθετήριο [SANDBOX]
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| URI | http://purl.tuc.gr/dl/dias/324FE72B-87A5-447F-931F-99D0EC29EB81 | - |
| Αναγνωριστικό | https://doi.org/10.1109/ICVD.2003.1183136 | - |
| Γλώσσα | en | - |
| Μέγεθος | 7 pages | en |
| Τίτλος | Processing and scheduling components in an innovative network processor architecture | en |
| Δημιουργός | Pnevmatikatos Dionysios | en |
| Δημιουργός | Πνευματικατος Διονυσιος | el |
| Δημιουργός | Nikoláou, Níkos A | en |
| Δημιουργός | S. Perissakis | en |
| Δημιουργός | T. Orphanoudakis | en |
| Δημιουργός | K. Vlachos | en |
| Περίληψη | In this paper, we describe the architecture of an innovative network processor aiming at the acceleration of packet processing in high speed network interfaces and at the tight coupling of low and high level protocols. The proposed design uses programmable hard-wired components with line rate throughput and is capable of executing protocols and handling efficiently high and low level streaming operations. We discuss the details of the main innovation of the proposed design, which incorporates a three stage RISC-based pipelined module and a composite scheduling unit for internal resource management and outgoing traffic shaping. When both components are integrated on the same platform then maximum and fair utilization of the available resources is achieved. Quantitative performance results are given, both by means of microcode profiling and simulation for indicative applications of the protocol processor. | en |
| Τύπος | Πλήρης Δημοσίευση σε Συνέδριο | el |
| Τύπος | Conference Full Paper | en |
| Άδεια Χρήσης | http://creativecommons.org/licenses/by/4.0/ | en |
| Ημερομηνία | 2015-10-19 | - |
| Ημερομηνία Δημοσίευσης | 2003 | - |
| Θεματική Κατηγορία | Monitoring of computer networks | en |
| Θεματική Κατηγορία | Network monitoring (Computer networks) | en |
| Θεματική Κατηγορία | computer networks monitoring | en |
| Θεματική Κατηγορία | monitoring of computer networks | en |
| Θεματική Κατηγορία | network monitoring computer networks | en |
| Βιβλιογραφική Αναφορά | K. Vlachos, T. Orphanoudakis, N. Nikolaou, S. Perissakis, D. Pnevmatikatos, G. Kornaros, J.A. Sanchez , G. Konstantoulakis, "Processing and scheduling components in an innovative network processor architecture’,"in 2003 Intern. Conf. on VLSI Design, pp.195 - 201.doi:10.1109/ICVD.2003.1183136 | en |
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