Το έργο με τίτλο An efficient and low-cost input/output subsystem for network processors από τον/τους δημιουργό/ούς Pnevmatikatos Dionysios, Kyriakos Vlachos, Ioannis Sourdis διατίθεται με την άδεια Creative Commons Αναφορά Δημιουργού 4.0 Διεθνές
Βιβλιογραφική Αναφορά
D. Pnevmatikatos, I. Sourdis , K. Vlachos,"An efficient and low-cost input/output subsystem for network processors .(2003).IEEE Design and Test of Computers [online]. pp. 56-64.Available:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.60.2374&rep=rep1&type=pdf
We present the architecture and implementation of an input/output subsystem for a cost-effective network processor. We believe that adding processing power to a networking chip is relatively straightforward. However, transferring data to and from the processor(s) is insufficient for high wire speeds. To address this limitation we use a hardwired input/output subsystem transferring data directly into the processing core’s register file. Using a simple scalar RISC core at 200MHz, we are able to sustain state-full inspection firewall processing at 2.5Gbps TCP traffic.