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Multisplitting iterative methods on fixed-size VLSI architectures

Saridakis Ioannis, Papadopoulou Eleni

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URIhttp://purl.tuc.gr/dl/dias/6046BEE3-CF4C-499F-B956-DB3163DBD5AC-
Identifierhttps://doi.org/10.1016/0956-0521(95)00036-4-
Languageen-
Extent8 pagesen
TitleMultisplitting iterative methods on fixed-size VLSI architecturesen
CreatorSaridakis Ioannisen
CreatorΣαριδακης Ιωαννηςel
CreatorPapadopoulou Elenien
CreatorΠαπαδοπουλου Ελενηel
PublisherElsevieren
Content SummaryMultisplitting Iterative Methods is a parametrizable family of iterative methods capable of solving Large Linear Systems. They are formed by the proper weighted average of classical (or not) iterative schemes. Hence, they present a second level of inherent parallelism while, at the same time, they take advantage of the parallel hardware to decrease both the computational time and the number of iterations involved in the computation. The increasingly large size of linear systems and the consideration of realistically large, but fixed-size, VLSI architectures, for their solution, motivated this work. We design new fixed size VLSI modules, based on space-time partitioning techniques, to efficiently resolve the problems arising in the computation of an oversized iteration step.en
Type of ItemPeer-Reviewed Journal Publicationen
Type of ItemΔημοσίευση σε Περιοδικό με Κριτέςel
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-10-16-
Date of Publication1995-
SubjectGreek mathematicsen
Subjectmathematics greeken
Subjectgreek mathematicsen
Bibliographic CitationE. P. Papadopoulou, Y. G. Saridakis, “Multisplitting iterative methods on fixed-size VLSI architectures," Comp. Syst. in Eng. ,vol.6 ,no. 4-5, pp. 477-484, 1995.doi:10.1016/0956-0521(95)00036-4en

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