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Run time system implementation for concurrent H/W S/W task execution on FPGA platforms

Koidis Iosif

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URIhttp://purl.tuc.gr/dl/dias/863B5FB2-A595-40B2-913B-DF4E1230A145-
Identifierhttps://doi.org/10.26233/heallink.tuc.26491-
Languageen-
Extent76 pagesen
TitleRun time system implementation for concurrent H/W S/W task execution on FPGA platformsen
CreatorKoidis Iosifen
CreatorΚοϊδης Ιωσηφel
Contributor [Thesis Supervisor]Pnevmatikatos Dionysiosen
Contributor [Thesis Supervisor]Πνευματικατος Διονυσιοςel
Contributor [Committee Member]Dollas Apostolosen
Contributor [Committee Member]Δολλας Αποστολοςel
Contributor [Committee Member]Samoladas Vasilisen
Contributor [Committee Member]Σαμολαδας Βασιληςel
PublisherTechnical University of Creteen
PublisherΠολυτεχνείο Κρήτηςel
Academic UnitTechnical University of Crete::School of Electronic and Computer Engineeringen
Academic UnitΠολυτεχνείο Κρήτης::Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστώνel
DescriptionΜεταπτυχιακή Διατριβή που υποβλήθηκε στην σχολή ΗΜΜΥ του Πολυτεχνείου Κρήτης για την πλήρωση προϋποθέσεων λήψης του Μεταπτυχιακού Διπλώματος Ειδίκευσηςel
Content SummaryIn the recent years, technology have made possible to fit a larger number of components on a single chip, and allowed us to realize larger, more complex chips. The large transistor budget can be used to create heterogeneous systems, generally called Multiprocessor Systems-on-Chip (MPSoC). It also allowed the creation of larger FPGA devices, integrating ample amounts of programmable logic, memories, programmable DSP/arithmetic units. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems, swapping in and out HW tasks. In this thesis we describe the integration process of a Run Time System Manager (RTSM) able to map multiple applications on the underlying architecture, which may consist of microprocessors as software processing elements and Partially Reconfigurable areas as hardware processing elements, and execute them concurrently. In this thesis we describe the integration process of a Run Time System Manager (RTSM) able to map multiple applications on the underlying architecture and execute them concurrently. The RTSM is able to schedule application tasks either on available processor core(s), or at the FPGA hardware resources using partial reconfiguration. The choice is made dynamically based on availability and a gain function VERIFY. We integrate and the RTSM on two different system architectures and corresponding platforms in order to demonstrate the RTSM portability and a real time application is used in order to validate its correctness and potential. The two aforementioned embedded platforms are the Xilinx XUPV5 board which hosts a Virtex 5 LX 110T device and the Zedboard platform which hosts a • Zynq®-7000 All Programmable SoC XC7Z020-CLG484-1.en
Type of ItemΜεταπτυχιακή Διατριβήel
Type of ItemMaster Thesisen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-06-17-
Date of Publication2015-
SubjectRun time system manageren
SubjectAdaptive computingen
SubjectConfigurable computing systemsen
SubjectReconfigurable computing systemsen
Subjectadaptive computing systemsen
Subjectadaptive computingen
Subjectconfigurable computing systemsen
Subjectreconfigurable computing systemsen
SubjectField programmable logic arraysen
SubjectFPGAsen
Subjectfield programmable gate arraysen
Subjectfield programmable logic arraysen
Subjectfpgasen
Bibliographic CitationIosif Koidis, "Run time system implementation for concurrent H/W S/W task execution on FPGA platforms", Master Thesis, School of Electronic and Computer Engineering, Technical University of Crete, Chania, Greece, 2015en
Bibliographic CitationΙωσήφ Κοΐδης, "Run time system implementation for concurrent H/W S/W task execution on FPGA platforms", Μεταπτυχιακή Διατριβή, Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών, Πολυτεχνείο Κρήτης, Χανιά, Ελλάς, 2015el

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