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Technical University of Crete
Technical University of Crete
EN
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EL
| URI | http://purl.tuc.gr/dl/dias/B8E60BAC-1C33-4023-AFBF-27A5DD9AA5D3 | - |
| Identifier | https://doi.org/10.26233/heallink.tuc.25751 | - |
| Language | en | - |
| Extent | 54 pages | en |
| Title | Implementation and evaluation of dynamic partial reconfiguration techniques on cryptographic algorithms | en |
| Creator | Kasabalis Vasileios | en |
| Creator | Κασαμπαλης Βασιλειος | el |
| Contributor [Thesis Supervisor] | Pnevmatikatos Dionysios | en |
| Contributor [Thesis Supervisor] | Πνευματικατος Διονυσιος | el |
| Contributor [Committee Member] | Dollas Apostolos | en |
| Contributor [Committee Member] | Δολλας Αποστολος | el |
| Contributor [Committee Member] | Koutroulis Eftychios | en |
| Contributor [Committee Member] | Κουτρουλης Ευτυχιος | el |
| Publisher | Πολυτεχνείο Κρήτης | el |
| Publisher | Technical University of Crete | en |
| Academic Unit | Πολυτεχνείο Κρήτης::Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών::Τομέας Ηλεκτρονικής και Αρχιτεκτονικής Υπολογιστών::Εργαστήριο Μικροεπεξεργαστών και Υλικού | el |
| Content Summary | In recent years the advantages of reconfigurable computing have make FPGAs important parts of many applications. One interesting characteristic of FPGAs is their ability to change parts of the design that runs on them dynamically. This procedure is called Partial Reconfiguration (PR). One disadvantage of PR is that sometimes it takes too much time to be completed and for real-time applications it has to be able to be executed fast. The purpose of this thesis is the implementation of designs that can perform PR with high throughput. When a reconfiguration is taken place a partial bitstream file must be transferred from a memory where it is stored to the reconfiguration memory of the FPGA. This transfer can be executed by software code that runs on a processor (e.g. PowerPC or MicroBlaze) or by hardware. For this thesis several designs were implemented, each one uses one of these methods to transfer the partial bitstream and a deferent memory where the partial bitstreams are stored. The memories that were used on these designs were a Compact Flash, a DDR2 SDRAM and a SRAM. The final result was a design that can perform PR with high throughput. | en |
| Type of Item | Διπλωματική Εργασία | el |
| Type of Item | Diploma Work | en |
| License | http://creativecommons.org/licenses/by-nc-nd/4.0/ | en |
| Date of Item | 2015-05-25 | - |
| Date of Publication | 2014 | - |
| Subject | Adaptive computing | en |
| Subject | Configurable computing systems | en |
| Subject | Reconfigurable computing systems | en |
| Subject | adaptive computing systems | en |
| Subject | adaptive computing | en |
| Subject | configurable computing systems | en |
| Subject | reconfigurable computing systems | en |
| Bibliographic Citation | Κασαμπαλής Βασίλειος, "Implementation and evaluation of dynamic partial reconfiguration techniques on cryptographic algorithms", Διπλωματική Εργασία, Τμήμα Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών, Πολυτεχνείο Κρήτης, 2015. | el |
| Bibliographic Citation | Vasileios Kasabalis, "Implementation and evaluation of dynamic partial reconfiguration techniques on cryptographic algorithms", Diploma Work, School of Electronic Computer Engineering, Technical University of Crete, Chania, Greece, 2014 | el |
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