Conference Publications

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	526-540 out of 1223 results
526	T. Orphanoudakis, G. Kornaros, H. Leligou, I. Papaefstathiou, S. Perissakis, N. Zervos. (2003,May). Scheduling components for multi-gigabit network SoCs. Presented at 2003 SPIE First International Symposium on Microtechnologies for the New Millennium. [Online]. Available: http://users.uop.gr/~fanis/html_files/pdf_files/papers/Conferences/C16_spie03_NPUsched.pdf	2015-11-16
527	G. Kornaros, I. Papaefstathiou, A. Nikologiannis, N. Zervos, "A fully programmable memory management system optimizing queue handling at multi gigabit rates," in 40th IEEE/ACM Design Automation Conference , 2003, pp. 54 - 59. doi: 10.1109/DAC.2003.1218800	2015-11-16
528	N. Mouratidis, G. Lykakis, A. Tavoularis, A. Kostopoulos, F. Petreas, D. Economou, A. Manousaridis, V. Vlaggoulis, I. Papaefstathiou, C. Georgopoulos, G. Konstantoulakis, "Convergence Processor: Standard and Custom IP in an Innovative SoC Design for Broadband Residential Applications," presented at IIIS International Conference on Computer, Communication and Control Technologies, 2003.	2015-11-16
529	I. Papaefstathiou, H. Leligou, T. Orphanoudakis, G. Kornaros, N. Zervos, G. Konstantoulakis, "An innovative scheduling scheme for high-speed network processors," in IEEE International Symposium on Circuits and Systems, 2003, pp. II-93 - II-96. doi: 10.1109/ISCAS.2003.1205899	2015-11-16
530	G. Kornaros, T. Orphanoudakis, I. Papaefstathiou, "GFS: an efficient implementation of fair scheduling for multigigabit packet networks," in 14th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2003), 2003, pp. 389 - 399. doi: 10.1109/ASAP.2003.1212862	2015-11-16
531	I. Papaefstathiou, C. Sotiriou. (2002,May). Read, Use, Simulate, Experiment and Build : An Integrated Approach for Teaching Computer Architecture. Presented at 8th Workshop on Computer Architecture Education (WCAE 2002), 29th International Symposium on Computer Architecture (ISCA 2002). [Online]. Available: https://www.ncsu.edu/wcae/ISCA2002/submissions/papaefstathiou.pdf	2015-11-16
532	I. Papaefstathiou, "An ultra high-speed compressor for packet networks," in 8th IEEE International Conference on Electronics, Circuits and Systems, 2001, pp. 1259 - 1263. doi: 10.1109/ICECS.2001.957444	2015-11-16
533	I. Papaefstathiou, "Measurement Based Connection Admission Control Algorithm for ATM Networks that Use Low Level Compression," in 7th International Conference on Intelligence in Services and Networks, ISandN 2000, pp. 49-60. doi: 10.1007/3-540-46525-1_4	2015-11-16
534	G. Kornaros, I. Papaefstathiou, "An Innovative Resource Management Scheme for Multi-gigabit Networking Systems," in 6th IEEE International Conference on High Speed Networks and Multimedia Communications, 2003, pp. 165-175. doi: 10.1007/978-3-540-45076-4_17	2015-11-16
535	T. Orphanoudakis, I. Papaefstathiou, G. Komaros, "Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors," in Proceedings of the 2003 International Symposium on Circuits and Systems, pp. II-97 - II-100 . doi: 10.1109/ISCAS.2003.1205901	2015-11-16
536	C. Sotiriou, I. Papaefstathiou, "A Design-Space Exploration of Alternative DES Implementations," presented at 10th IEEE International Conference on Electronics, Circuits and Systems, Sharja, U.A.E., 2003.	2015-11-16
537	I. Papaefstathiou, "Titan II: an IPComp processor for 10Gbit/sec networks," in IEEE Computer Society Annual Symposium on VLSI, 2003, pp. 234 - 235. doi: 10.1109/ISVLSI.2003.1183479	2015-11-16
538	M. Katevenis, G. Passas, D. Simos, I. Papaefstathiou and N. Chrysos, "Variable packet size buffered crossbar (CICQ) switches," presented at IEEE International Conference on Communications, Paris, France, 2004.	2015-11-16
539	I. Papaefstathiou, D. Pnevmatikatos, V. Dimopoulos, "A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems," in International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2007, pp. 186 - 193. doi: 10.1109/ICSAMOS.2007.4285750	2015-11-16
540	I. Papaefstathiou, V. Papaefstathiou, "Memory-Efficient 5D Packet Classification At 40 Gbps," in 26th IEEE International Conference on Computer Communications2007, pp. 1370 - 1378. doi: 10.1109/INFCOM.2007.162	2015-11-16
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