Institutional Repository [SANDBOX]
Technical University of Crete
EN  |  EL

Search

Browse

My Space

Reliable runtime architecture for multiprocessor systems on chip

Skarlatos Dimitrios

Simple record


URIhttp://purl.tuc.gr/dl/dias/58F95797-B712-4999-9DDE-F2FC5A8CB56C-
Identifierhttps://doi.org/10.26233/heallink.tuc.17741-
Languageen-
Extent60 pagesen
TitleReliable runtime architecture for multiprocessor systems on chipen
CreatorSkarlatos Dimitriosen
CreatorΣκαρλατος Δημητριοςel
Contributor [Thesis Supervisor]Pnevmatikatos Dionysiosen
Contributor [Thesis Supervisor]Πνευματικατος Διονυσιοςel
Contributor [Committee Member]Dollas Apostolosen
Contributor [Committee Member]Δολλας Αποστολοςel
Contributor [Committee Member]Papaefstathiou Ioannisen
Contributor [Committee Member]Παπαευσταθιου Ιωαννηςel
Contributor [Co-Supervisor]Πρατικάκης Πολύβιοςel
Contributor [Co-Supervisor]Pratikakis Polyviosen
PublisherΠολυτεχνείο Κρήτηςel
PublisherTechnical University of Creteel
Academic UnitΠολυτεχνείο Κρήτης::Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστώνel
DescriptionΠροπτυχιακή Διατριβή που υποβλήθηκε στη σχολή ΗΜΜΥ του Πολ. Κρήτης για την πλήρωση προϋποθέσεων λήψης του Προπτυχιακού Διπλώματος Ειδίκευσης.el
Content SummaryMission critical applications rely on both hardware- and software-approaches for fault-tolerance. With the adoption of multiprocessor systems on chip (MPSoCs), processor fault-tolerance with modular redundancy has become a major issue, cost and performance wise. In this thesis first , we augment a task-parallel runtime system with support for transparent checkpoints of task data that may be written during task execution and seamlessly rerun failed tasks. The system can recover from transient errors during task execution within a single core by rerunning the failed task, as well as from permanent errors that disable a worker core by redistributing work among remaining cores. We have evaluated our implementation using six benchmarks and found that checkpointing incurs a performance overhead of 8\% on average, mainly due to the cost of memory copies, and only a negligible space overhead due to the recycling of checkpoint memory. Then, in order to protect the workers runtime system beyond the execution stage, we present ASGUARDIAN, a lightweight hardware mechanism based on a task-oriented model for general programmability. The ASGUARDIAN features both store-and-forward and cut-through capabilities to reliably transfer task descriptions and arguments between main memory and available worker cores. It also isolates the workers from accessing the main memory. A hardware prototype has been implemented on a Xilinx ML605 FPGA board using the widely-used ARM AMBA protocol. Introducing the ASGUARDIAN reliability features results in a 8% average overhead on hardware resources for a configuration with four Microblaze cores. The performance overhead for the store-and-forward and cut-through implementations were 2.3x and 1.2x respectively against an unprotected, shared memory system. When compared against an -unprotected- scratchpad-based memory system, the store-and-forward version showed an overhead of 1.7x, while the cut-through version showed a speedup of 6% on average.en
Type of ItemΔιπλωματική Εργασίαel
Type of ItemDiploma Worken
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2014-06-03-
Date of Publication2014-
SubjectComputing, Fault-toleranten
Subjectfault tolerant computingen
Subjectcomputing fault toleranten
SubjectComputer reliabilityen
Subjectcomputers reliabilityen
Subjectcomputer reliabilityen
SubjectCLR (Common Language Runtime)en
Subjectcommon language runtime computer scienceen
Subjectclr common language runtimeen
SubjectSOC designen
SubjectSystems on chipen
Subjectsystems on a chipen
Subjectsoc designen
Subjectsystems on chipen
SubjectMulticoresen
SubjectTask Based Programming Modelen
SubjectField programmable logic arraysen
SubjectFPGAsen
Subjectfield programmable gate arraysen
Subjectfield programmable logic arraysen
Subjectfpgasen
Bibliographic CitationDimitrios Skarlatos, "Reliable runtime architecture for multiprocessor systems on chip", Diploma Work, School of Electronic Engineering, Technical University of Crete, Chania, Greece, 2014el
Bibliographic CitationΔημήτριος Σκαρλάτος, "Reliable runtime architecture for multiprocessor systems on chip", Διπλωματική Εργασία, Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών, Πολυτεχνείο Κρήτης, Χανιά, Ελλάς, 2014el

Available Files

Services

Statistics