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School of Electrical and Computer Engineering

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Automation Laboratory Circuits, Sensors and Renewable Energy Sources Laboratory Digital Image and Signal Processing Laboratory Distributed Multimedia Information Systems and Applications Laboratory Electric Energy Systems Laboratory Electronics Laboratory Information and Networks Laboratory Intelligent Systems Laboratory Microprocessor and Hardware Laboratory Software Technology and Network Applications Laboratory Telecommunications Laboratory

Other Items Books and Book Chapters Journal Publications Conference Publications Doctoral Dissertations Diploma Works Learning Material Scientific and Experimental Datasets Master Theses

Last Submissions

	1861-1875 out of 4222 results
1861	I. Papaefstathiou, " Low-level Hardware Compression for Multi-Gigabit Networks," Journal of Circuits, Systems and Computers, vol. 13, no. 6, pp. 1307-1319, Dec. 2004. doi: 10.1142/S0218126604001969	2015-11-16
1862	I. Papaefstathiou, "Titan II: an IPComp processor for 10Gbit/sec networks," IEEE Design and Test (DandT)., pp. 234 - 235, Nov. 2004. doi:10.1109/ISVLSI.2003.1183479	2015-11-16
1863	I. Papaefstathiou, V. Papaefstathiou, C. Sotiriou, "Elsevier Journal on Microprocessors and Microsystems," vol. 28, no. 10, pp. 561-571, Sept. 2013. doi:10.1016/j.micpro.2004.08.009	2015-11-16
1864	I. Papaefstathiou. (2000,May). A complete framework for on-line Compression of ATM streams. Presented at IEEE/IEE International Conference on Telecommunications 2000. [Online]. Available: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.20.344&rep=rep1&type=pdf	2015-11-16
1865	I. Papaefstathiou, "Accelerating ATM: on-line compression of ATM streams," in 18th IEEE International Performance, Computing, and Communications Conference, 1999, pp. 233 - 239. doi: 10.1109/PCCC.1999.749443	2015-11-16
1866	I. Papaefstathiou, "Compressing ATM streams on-line," in 1999 IEEE Data Compression Conference, 1999. doi: 10.1109/DCC.1999.785700	2015-11-16
1867	A. Brown, D. Chian, N. Mehta, I. Papaefstathiou, J. Simer, T. Blackwell, M. Smith, W. Yang. (1997,June). Using MML to Simulate Multiple Dual-Ported SRAMs: Parallel Routing Lookups in an ATM Switch Controller. Presented at Workshop on Mixing Logic and DRAM, International Symposium of Computer Architecture. [Online]. Available: http://www.126doc.com/p-4098460.html	2015-11-16
1868	I. Papaefstathiou, A. Brown, J. Simer, D. Sobel, J. Sutaria, Y. WangT. Blackwell, M. Smith, W. Yang, "An IRAM-based architecture for a single-chip ATM switch," in 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, pp. 97 - 100. doi: 10.1109/ICECS.1999.812232	2015-11-16
1869	I. Papaefstathiou, G. Kornaros, N. Zervos, "Software processing performance in network processors," in IEEE Design Automation and Test in Europe, 2004, pp. 186 - 191. doi: 10.1109/DATE.2004.1269228	2015-11-16
1870	T. Orphanoudakis, G. Kornaros, H. Leligou, I. Papaefstathiou, S. Perissakis, N. Zervos. (2003,May). Scheduling components for multi-gigabit network SoCs. Presented at 2003 SPIE First International Symposium on Microtechnologies for the New Millennium. [Online]. Available: http://users.uop.gr/~fanis/html_files/pdf_files/papers/Conferences/C16_spie03_NPUsched.pdf	2015-11-16
1871	G. Kornaros, I. Papaefstathiou, A. Nikologiannis, N. Zervos, "A fully programmable memory management system optimizing queue handling at multi gigabit rates," in 40th IEEE/ACM Design Automation Conference , 2003, pp. 54 - 59. doi: 10.1109/DAC.2003.1218800	2015-11-16
1872	N. Mouratidis, G. Lykakis, A. Tavoularis, A. Kostopoulos, F. Petreas, D. Economou, A. Manousaridis, V. Vlaggoulis, I. Papaefstathiou, C. Georgopoulos, G. Konstantoulakis, "Convergence Processor: Standard and Custom IP in an Innovative SoC Design for Broadband Residential Applications," presented at IIIS International Conference on Computer, Communication and Control Technologies, 2003.	2015-11-16
1873	I. Papaefstathiou, H. Leligou, T. Orphanoudakis, G. Kornaros, N. Zervos, G. Konstantoulakis, "An innovative scheduling scheme for high-speed network processors," in IEEE International Symposium on Circuits and Systems, 2003, pp. II-93 - II-96. doi: 10.1109/ISCAS.2003.1205899	2015-11-16
1874	G. Kornaros, T. Orphanoudakis, I. Papaefstathiou, "GFS: an efficient implementation of fair scheduling for multigigabit packet networks," in 14th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2003), 2003, pp. 389 - 399. doi: 10.1109/ASAP.2003.1212862	2015-11-16
1875	I. Papaefstathiou, C. Sotiriou. (2002,May). Read, Use, Simulate, Experiment and Build : An Integrated Approach for Teaching Computer Architecture. Presented at 8th Workshop on Computer Architecture Education (WCAE 2002), 29th International Symposium on Computer Architecture (ISCA 2002). [Online]. Available: https://www.ncsu.edu/wcae/ISCA2002/submissions/papaefstathiou.pdf	2015-11-16
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